Compact and Secure Generic Discrete Gaussian Sampler based on HW/SW Co-design

In this paper, we present the first Hardware (HW) / Software (SW) co-design based generic discrete Gaussian sampler architecture on the Xilinx Zynq platform. The area optimized and secure sampler can produce a distribution based on an arbitrary standard deviation and center given as input. We use multi-level logic optimization on Knuth-Yao algorithm's Discrete Distribution Generating (DDG) tree travel-based Boolean mapping of random bits and samples instead of the previous two-level logic optimization to reduce the resource utilization. This method results in nearly 60% lesser LUT utilization compared to the previous designs on Xilinx FPGAs. Further, we introduce improvements in the shuffling algorithm leveraging the HW/SW co-design methodology compared to the existing shuffling architectures for randomizing Gaussian samples to protect against timing-based side-channel attacks.