RaceR: A Thread Mapping Algorithm for Race Reduction in Multi-Level Shared Caches

Multi-level hierarchical cache architectures are now being widely used in the design and fabrication of multi and many-core chips. However, when two or more threads race to write their own data into the shared-cache, contentions may happen. This natural conflict seriously aggravates the performance of multi-core systems by showing variant performance in multiple runs of even a same program. In this paper, an efficient thread-mapping algorithm is proposed to minimize the cache race condition between threads of multi-core systems. The proposed algorithm, dynamically monitors races on cache blocks and distributes existing and new threads on cores such that the cache contention is minimized. The proposed algorithm uses instructions per cycle (IPC) parameter to detect conflicting threads on the multi-core system. Upon detection of a high contention rate, two mechanisms of cache access rate reduction, and thread migration are used to resolve the race situation. The first solution is a short term one with negligible performance loss, while the former totally resolves the problem with a relatively higher performance cost. Evaluations of the proposed algorithm are done by the use of AKULA simulator alongside SPEC CPU 2006 benchmark suit. Simulation results show that the proposed algorithm improves system performance by average of 6.12% for the SPEC CPU 2006 benchmark suit.