Bit-width Optimization of Extrinsic Information in Turbo Decoder

Soft Input Soft Output (SISO) decoders iteratively exchanging intermediate results (extrinsic information) between themselves lie at the core of turbo decoder architectures. The implementation architecture could be serial, parallel or network on chip (NoC) based. In this paper, we present a technique for bit-width reduction of exchanged extrinsic information and analyze the impact of it for different implementation architectures. The methodology is investigated over two kinds of turbo decoding system, both based on the Max-Log-MAP algorithm. First is a serial concatenated convolutional code (SCCC) decoder and the other is a WiMax (IEEE 802.16e) parallel concatenated convolutional code (PCCC) decoder. For the SCCC decoder, bitwidth of the extrinsic information can be reduced from 8 bits down to 4 without significant bit-error-rate (BER) degradation. For the WiMax case it can be reduced from 8 bits down to 5 with a BER degradation of 0.2 dB.