共 50 条
- [1] A case for visualization-integrated system-level design space exploration [J]. EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING, AND SIMULATION, 2005, 3553 : 455 - 464
- [2] Formal system-level design space exploration [J]. CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE, 2013, 25 (02): : 250 - 264
- [3] Data Mining in System-Level Design Space Exploration of Embedded Systems [J]. EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING, AND SIMULATION, SAMOS 2020, 2020, 12471 : 52 - 66
- [4] System-level MP-SoC Design Space Exploration Using Tree Visualization [J]. 2009 IEEE/ACM/IFIP 7TH WORKSHOP ON EMBEDDED SYSTEMS FOR REAL-TIME MULTIMEDIA, 2009, : 80 - 88
- [5] System-level computer architecture simulation: An experiment report [J]. 1977 IEEE INTERNATIONAL PERFORMANCE, COMPUTING AND COMMUNICATIONS CONFERENCE, 1997, : 284 - 290
- [6] Perspectives on System-level MPSoC Design Space Exploration [J]. PROCEEDINGS OF 2016 INTERNATIONAL CONFERENCE ON EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING AND SIMULATION (SAMOS), 2016, : 335 - 335
- [7] A methodology for system-level analog design space exploration [J]. DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2004, : 676 - 677
- [8] A mixed-level co-simulation method for system-level design space exploration [J]. PROCEEDINGS OF THE 2006 IEEE/ACM/IFIP WORKSHOP ON EMBEDDED SYSTEMS FOR REAL TIME MULTIMEDIA, 2006, : 27 - +
- [9] ArchSim: A System-Level Parallel Simulation Platform for the Architecture Design of High Performance Computer [J]. Journal of Computer Science and Technology, 2009, 24 : 901 - 912