A scalable packet sorting circuit for high-speed WFQ packet scheduling

被引：1
|
作者：
McLaughlin, K. [1 ]
Sezer, S. [1 ]
Blume, H. [2 ]
Yang, X. [1 ]
Kupzog, F. [2 ]
Noll, T. [2 ]
机构：
[1] Queens Univ Belfast, Inst Elect Commun & Informat, Belfast BT7 1NN, Antrim, North Ireland
[2] Rhein Westfal TH Aachen, Elect Engn & Comp Syst, D-52056 Aachen, Germany
来源：
IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | 2006年
关键词：
D O I：
10.1109/SOCC.2006.283896
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A novel implementation of a tag sorting circuit for a Weighted Fair Queuing (WFQ) enabled IP packet scheduler is presented. The design consists of a search tree, matching circuitry and a custom memory layout. The implementation uses 130nm silicon technology and supports Quality of Service on networks at line speeds of 40Gbps.
引用
收藏
页码：271 / +
页数：2
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