Universal NBTI Compact Model for Circuit Aging Simulation under Any Stress Conditions

被引：36

作者：

Ma, Chenyue ^{[1
]}

Mattausch, Hans Juergen ^{[1
]}

Matsuzawa, Kazuya ^{[2
]}

Yamaguchi, Seiichiro ^{[2
]}

Hoshida, Teruhiko ^{[2
]}

Imade, Masahiro ^{[2
]}

Koh, Risho ^{[2
]}

Arakawa, Takahiko ^{[2
]}

Miura-Mattausch, Mitiko ^{[1
]}

机构：

[1] Hiroshima Univ, Grad Sch Adv Sci Matter, Hiroshima 7398530, Japan

[2] Semicond Technol Acad Res Ctr, Yokohama, Kanagawa 2220033, Japan

来源：

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY | 2014年 / 14卷 / 03期

基金：

日本学术振兴会;

关键词：

Negative bias temperature instability (NBTI); modeling; interface-state; hole-trapping; universality; BIAS TEMPERATURE-INSTABILITY; INTERFACE-TRAP; DEGRADATION; GENERATION; DEPENDENCE; MECHANISMS; BEHAVIOR;

D O I：

10.1109/TDMR.2014.2322673

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a compact model for the negative bias temperature instability (NBTI) is developed by considering the interface-state generation and the hole-trapping mechanisms. This model shows accurate reproduction of the threshold voltage (V-th) degradations measured from samples fabricated with different dielectric materials as well as processes. A total of eight model parameters are introduced for describing the different degradation origins. The parameter values are verified to exhibit universal properties as a function of the electrical field within the gate oxide (E-ox). By implementing the universal NBTI model into the compact model HiSIM, the dynamic NBTI effect and circuit performance degradation can be predicted.

引用

页码：818 / 825

页数：8

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