DC-40 GHz SPDTs in 22 nm FD-SOI and Back-Gate Impact Study

被引：0
|
作者：
Rack, Martin [1 ]
Nyssens, Lucas [1 ]
Wane, Sidina [2 ]
Bajon, Damienne [2 ]
Raskin, Jean-Pierre [1 ]
机构：
[1] Catholic Univ Louvain, Dept Elect Engn, Louvain, Belgium
[2] eV Technol, Caen, France
来源：
2020 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM (RFIC) | 2020年
关键词：
SPDT; switch; ultra-wideband; millimeter-wave IC; 5G front-end; FD SOI; UTBB; back-gate bias; linearity; IIP3; CMOS;
D O I：
10.1109/rfic49505.2020.9218317
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, ultra-wideband SPDTs fabricated in the 22 nm FD-SOI process from GLOBALFOUNDRIES are presented. Three SPDT modules were implemented, each using a different type of millimeter-wave NFET, namely a conventionalwell regular-Vt (RVT) device, a flipped-well super-low-Vt (SLVT) device and a specially treated device without back-gate well contact for decreased substrate parasitics (BFMOAT device). It is shown that using the back-gate achieves lower losses, higher isolation and better linearity for the RVT and SLVT based switches, while the reduced parasitic BFMOAT switch shows better performance at the high-end of the mm-wave spectrum.
引用
收藏
页码：67 / 70
页数：4
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