Power aware memory management for embedded systems

This paper proposes a method of electric power aware memory management of embedded operating systems. The target hardware system we consider in this paper consists of a single chip containing a processor and internal memory (say on-chip memory), a chip containing external memory (say offchip memory), and DMA (Direct Memory Access). Total memory including the on-chip memory and the off-chip one constitutes a linear physical address space. These memories have different electric characteristics. Load and store accesses to the on-chip memory are executed fast and with low power. On the other hand, load and store accesses to the off-chip memory are executed slowly and with high power, because of the influence of the external other circuits. In addition, our hardware system is assumed to provide two power modes of the off-chip memory to software (memory management in an operating system), high mode and low one. That is, memory management can control the state of the power mode of the off-chip memory. This paper proposes a method of electric power saving by dynamically combining paging between the on-chip memory and the off-chip one with changing the state of the off-chip memory power mode. Through simulation experiments, the pro-posed method is shown to save the power.