A design and implementation of reconfigurable architecture for neural networks based on systolic arrays

This paper proposes a reconfigurable architecture for VLSI implementation of BP neural networks with on-chip learning. Basing on systolic arrays, this architecture can flexibly adapt to neural networks with different scales, transfer functions or learning algorithms by reconfiguration of basic processing components,. Three kinds of reconfigurable processing units (RPU) are proposed firstly basing on the analysis of neural network's reconfiguration. Secondly, the paper proposes a reconfigurable systolic architecture and the method of mapping BP networks into this architecture. The implementation of an instance on FPGA is introduced in the last. The results show that this flexible architecture can also achieve a high learning speed of 432M CUPS (Connection Updated Per Second) at 100MHz using 22 multipliers.