FPGA implementation of the conjugate gradient method

The rational fraction number system is proposed to solve the algebraic problems in FPGA devices. The fraction number consists of the n-bit integer numerator and the n-bit integer denominator, and can represent numbers with 2n bit mantissa. Experimental linear equation system solver was developed in FPGA device, which implements the recursive conjugate gradient method. Its hardware arithmetic unit can calculate addition, multiplication, and division of fraction numbers with n=35 in a pipelined mode. The proposed unit operates with the band matrices with the dimensions up to 3500.