FPGA implementation of the conjugate gradient method

被引：0
|
作者：
Maslennikow, Oleg
Lepekha, Volodymyr
Sergyienko, Anatoli
机构：
[1] Tech Univ Koszalin, PL-75453 Koszalin, Poland
[2] Natl Tech Univ Ukraine, UA-03056 Kiev, Ukraine
来源：
PARALLEL PROCESSING AND APPLIED MATHEMATICS | 2006年 / 3911卷
关键词：
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
The rational fraction number system is proposed to solve the algebraic problems in FPGA devices. The fraction number consists of the n-bit integer numerator and the n-bit integer denominator, and can represent numbers with 2n bit mantissa. Experimental linear equation system solver was developed in FPGA device, which implements the recursive conjugate gradient method. Its hardware arithmetic unit can calculate addition, multiplication, and division of fraction numbers with n=35 in a pipelined mode. The proposed unit operates with the band matrices with the dimensions up to 3500.
引用
收藏
页码：526 / 533
页数：8
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