MGSim-A Simulation Environment for Multi-Core Research and Education

被引:0
|
作者
Poss, Raphael [1 ]
Lankamp, Mike [1 ]
Yang, Qiang [1 ]
Fu, Jian [1 ]
Uddin, Irfan [1 ]
Jesshope, Chris R. [1 ]
机构
[1] Univ Amsterdam, Comp Syst Architecture Grp, NL-1098 XH Amsterdam, Netherlands
来源
2013 INTERNATIONAL CONFERENCE ON EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING AND SIMULATION (IC-SAMOS) | 2013年
关键词
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中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This article presents MGSim(1), an open source discrete event simulator for on-chip hardware components developed at the University of Amsterdam. MGSim is used as research and teaching vehicle to study the fine-grained hardware/software interactions on many-core chips with and without hardware multithreading. MGSim's component library includes support for core models with different instruction sets, a configurable interconnect, multiple configurable cache and memory models, a dedicated I/O subsystem, and comprehensive monitoring and interaction facilities. The default model configuration shipped with MGSim implements Microgrids, a multi-core architecture with hardware concurrency management. MGSim is furthermore written mostly in C++ and uses object classes to represent chip components. It is optimized for architecture models that can be described as process networks.
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收藏
页码:80 / 87
页数:8
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