Estimating phase-locked loop jitter due to substrate coupling: A cyclostationary approach

被引：0

作者：

Chan, HHY ^{[1
]}

Zilic, Z ^{[1
]}

机构：

[1] McGill Univ, Dept ECE, Microelect & Comp Syst Lab, Montreal, PQ H3A 2A7, Canada

来源：

ISQED 2004: 5TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS | 2004年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

On-chip phase-locked loops (PLLs) are critical components for clock generation and recovery in high-speed communication and data processing systems. The presence of partially-correlated substrate noise presents a new challenge to predicting PLL jitter. We propose a model that describes the substrate noise-to-jitter transfer characteristics for CMOS ring oscillator-based PLLs on epitaxial substrate. The proposed model is verified against jitter simulations.

引用

页码：309 / 314

页数：6

共 50 条

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