A Frequency Synthesizer Based on Zero-Crossing Digital Phaselocked Loop

被引：0

作者：

Salahat, Ehab ^{[1
]}

Al-Araji, Saleh R. ^{[1
]}

Al-Qutayri, Mahmoud ^{[1
]}

机构：

[1] Khalifa Univ, Coll Engn, Abu Dhabi, U Arab Emirates

来源：

2013 IEEE 20TH INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS, AND SYSTEMS (ICECS) | 2013年

关键词：

Zero-Crossing Digital Phaselocked Loop; Frequency Synthesizers; Hybrid Divider; Finite State Machine;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents an efficient hybrid frequency synthesizer, that is capable of both integer and fractional division, design based on the Zero-Crossing Digital Phase-locked Loop architecture. The design uses an efficient adaptation mechanism to maintain the in-lock state following the division process. The fast switching, locking and acquisition of the system make it an excellent candidate for synthesis even in Doppler environment. The simulation results demonstrate that the proposed synthesizer can achieve the desired frequency division.

引用

页码：835 / 838

页数：4

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