Scaling Split-Gate Flash Memory Technology for Advanced MCU and Emerging Applications

被引：2

作者：

Do, N. ^{[1
]}

Kim, J. ^{[1
]}

Lemke, S. ^{[1
]}

Tee, L. ^{[1
]}

Tkachev, Y. ^{[1
]}

Liu, X. ^{[1
]}

Ghazavi, P. ^{[1
]}

Zhou, F. ^{[1
]}

Villard, B. ^{[1
]}

Jourba, S. ^{[1
]}

Decobert, C. ^{[1
]}

Hong, S. ^{[1
]}

Vu, T. ^{[1
]}

Trinh, S. ^{[1
]}

Ly, A. ^{[1
]}

Tran, H. ^{[1
]}

Tiwari, V. ^{[1
]}

Reiten, M. ^{[1
]}

机构：

[1] Silicon Storage Technol Inc, San Jose, CA 95134 USA

来源：

2019 IEEE 11TH INTERNATIONAL MEMORY WORKSHOP (IMW 2019) | 2019年

关键词：

D O I：

10.1109/imw.2019.8739270

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, scaling prospects and challenges of embedded split-gate SuperFlash (R) ( ESF) technology to 28 nm and below are discussed. The integration of the inherent HKMG in the select transistor of the split-gate memory cell ESF3 enhances the cell performance without compromising its reliability and results in lowering the embedded flash process cost. This result also paves the way for a conceptual ease of integrating ESF cell into a FinFET CMOS process node. This paper will also demonstrate the capability and performance of subthreshold current tuning of the 28 nm split-gate SuperFlash (R) cell and its potential implementation in analog computing applications.

引用

页码：28 / 31

页数：4

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