Automatic control flow generation for OpenVX graphs

Heterogeneous platforms with large numbers of processing elements (PEs) have been proposed to satisfy the computational requirements of computer vision applications. Limiting the incurred communication cost here is key to meet the power constraints of embedded devices. We present a new heuristic to reduce communication among PEs and to external memory by aggregating inter-process communication and pipelining image processing functions. The application is specified as an OpenVX graph, an industry standard for vision applications, though our method is applicable to dataflow in general. We use dataflow and graph-based analysis techniques to map the application at configuration time to a hardware platform with strong program memory constraints. We show that our approach can yield a reduction of up to 53% in communication compared to other OpenVX implementations.