Design, implementation and testing of the controller for the terabit packet switch

被引：1

作者：

Petrovic, Milos ^{[1
]}

Blagojevic, Milos ^{[1
]}

Smiljanic, Aleksandra ^{[1
,2
]}

Jokovic, Vladimir ^{[1
]}

机构：

[1] Univ Belgrade, Belgrade, Serbia

[2] SUNY Stony Brook, New York, NY USA

来源：

2006 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLS 1-4: VOL 1: SIGNAL PROCESSING | 2006年

关键词：

D O I：

10.1109/ICCCAS.2006.285001

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

The sequential greedy scheduling (SGS) is a scalable algorithm that provides non-blocking in high-capacity packet switches. We implemented the SGS scheduler in the FPGA device, and examined its scalability and speed. Then, we developed the software for design testing. Our testing software confirms the correct functioning of the scheduler. Both, the scheduler implementation, and the testing software are presented in this paper.

引用

页码：1701 / +

页数：2

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