ACCDSE: A Design Space Exploration Framework for Convolutional Neural Network Accelerator

被引:2
|
作者
Li, Zhisheng [1 ]
Wang, Lei [1 ]
Dou, Qiang [1 ]
Tang, Yuxing [1 ]
Guo, Shasha [1 ]
Zhou, Haifang [1 ]
Lu, Wenyuan [2 ]
机构
[1] Natl Univ Def Technol, Changsha, Hunan, Peoples R China
[2] Xian Satellite Monitoring & Control Ctr, Xian, Shaanxi, Peoples R China
关键词
CNN; Design space exploration; Data precision Accelerator; Weight pruning;
D O I
10.1007/978-981-10-7844-6_3
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
In deep learning, convolutional neural network (CNN) is quite representative. The convolutional operation of CNN is the focus of hardware acceleration research. Because of CNN's memory-intensive and compute-intensive features, increasing size of network poses a greater challenge on the design of the hardware accelerator. We need to determine the parameters of the accelerator at the early stages of the accelerator design. This paper presents a design space exploration framework for CNN accelerator: ACCDSE, for determining the parameters of convolutional accelerator in FPGA. Simulation method and theoritical computation method are both used to find the optimal parameter. Experiment on LeNet shows that 16-bit fixed point is the most economical data precision for inference of LeNet. By theoritical analysis, the ACCDSE framework can obtain optimal matrix tiling parameters. Without decreasing the classification accuracy, the power consumption can be reduced by 33.57% and the storage can be reduced by 41.47% after weight pruning.
引用
收藏
页码:22 / 34
页数:13
相关论文
共 50 条
  • [1] Design Space Exploration for YOLO Neural Network Accelerator
    Huang, Hongmin
    Liu, Zihao
    Chen, Taosheng
    Hu, Xianghong
    Zhang, Qiming
    Xiong, Xiaoming
    [J]. ELECTRONICS, 2020, 9 (11) : 1 - 15
  • [2] Design space exploration of neural network accelerator based on transfer learning
    吴豫章
    ZHI Tian
    SONG Xinkai
    LI Xi
    [J]. High Technology Letters, 2023, 29 (04) : 416 - 426
  • [3] Design of a Safe Convolutional Neural Network Accelerator
    Xu, Zheng
    Abraham, Jacob
    [J]. 2019 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI 2019), 2019, : 248 - 253
  • [4] A Design Space Exploration Framework for Convolutional Neural Networks Implemented on Edge Devices
    Tsimpourlas, Foivos
    Papadopoulos, Lazaros
    Bartsokas, Anastasios
    Soudris, Dimitrios
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2018, 37 (11) : 2212 - 2221
  • [5] GANDSE: Generative Adversarial Network-based Design Space Exploration for Neural Network Accelerator Design
    Feng, Lang
    Liu, Wenjian
    Guo, Chuliang
    Tang, Ke
    Zhuo, Cheng
    Wang, Zhongfeng
    [J]. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2023, 28 (03)
  • [6] Improving Performance Estimation for Design Space Exploration for Convolutional Neural Network Accelerators
    Ferianc, Martin
    Fan, Hongxiang
    Manocha, Divyansh
    Zhou, Hongyu
    Liu, Shuanglong
    Niu, Xinyu
    Luk, Wayne
    [J]. ELECTRONICS, 2021, 10 (04) : 1 - 14
  • [7] Design Space Exploration Scheme for Mapping Convolutional Neural Network on Zynq Zedboard
    Ul Hassan, M. Sohaib
    Khan, Umar S.
    Khawaja, Sajid Gul
    [J]. PROCEEDINGS OF THE 2020 12TH INTERNATIONAL CONFERENCE ON ELECTRONICS, COMPUTERS AND ARTIFICIAL INTELLIGENCE (ECAI-2020), 2020,
  • [8] Convolutional Neural Network (CNN) Accelerator Chip Design
    Ma, Xinran
    Zhao, Ruiyong
    Zhou, Jianyang
    [J]. PROCEEDINGS OF 2019 IEEE 13TH INTERNATIONAL CONFERENCE ON ANTI-COUNTERFEITING, SECURITY, AND IDENTIFICATION (IEEE-ASID'2019), 2019, : 211 - 215
  • [9] Accelerator Design for Vector Quantized Convolutional Neural Network
    Wu, Yi-Heng
    Lee, Heng
    Lin, Yu Sheng
    Chien, Shao-Yi
    [J]. 2019 IEEE INTERNATIONAL CONFERENCE ON ARTIFICIAL INTELLIGENCE CIRCUITS AND SYSTEMS (AICAS 2019), 2019, : 46 - 50
  • [10] Design and Implementation of a Universal Shift Convolutional Neural Network Accelerator
    Song, Qingzeng
    Cui, Weizhi
    Sun, Liankun
    Jin, Guanghao
    [J]. IEEE EMBEDDED SYSTEMS LETTERS, 2024, 16 (01) : 17 - 20