A Design Space Exploration Framework for Convolutional Neural Networks Implemented on Edge Devices

被引:14
|
作者
Tsimpourlas, Foivos [1 ]
Papadopoulos, Lazaros [1 ]
Bartsokas, Anastasios [1 ]
Soudris, Dimitrios [1 ]
机构
[1] Natl Tech Univ Athens, Sch Elect & Comp Engn, Zographou Campus, Athens 15780, Greece
关键词
Convolutional neural networks (CNNs); design space exploration (DSE); embedded systems;
D O I
10.1109/TCAD.2018.2857280
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Deploying convolutional neural networks (CNNs) in embedded devices that operate at the edges of Internet of Things (IoT) networks provides various advantages in terms of performance, energy efficiency, and security in comparison with the alternative approach of transmitting large volumes of data for processing to the cloud. However, the implementation of CNNs on low power embedded devices is challenging due to the limited computational resources they provide and to the large resource requirements of state-of-the-art CNNs. In this paper, we propose a framework for the efficient deployment of CNNs in low power processor-based architectures used as edge devices in IoT networks. The framework leverages design space exploration (DSE) techniques to identify efficient implementations in terms of execution time and energy consumption. The exploration parameter is the utilization of hardware resources of the edge devices. The proposed framework is evaluated using a set of 6 state-of-the-art CNNs deployed in the Intel/Movidius Myriad2 low power embedded platform. The results show that using the maximum available amount of resources is not always the optimal solution in terms of performance and energy efficiency. Fine-tuned resource management based on DSE, reduces the execution time up to 3.6% and the energy consumption up to 7.7% in comparison with straightforward implementations.
引用
收藏
页码:2212 / 2221
页数:10
相关论文
共 50 条
  • [1] Design Space Exploration of FPGA Accelerators for Convolutional Neural Networks
    Rahman, Atul
    Oh, Sangyun
    Lee, Jongeun
    Choi, Kiyoung
    [J]. PROCEEDINGS OF THE 2017 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2017, : 1147 - 1152
  • [2] ACCDSE: A Design Space Exploration Framework for Convolutional Neural Network Accelerator
    Li, Zhisheng
    Wang, Lei
    Dou, Qiang
    Tang, Yuxing
    Guo, Shasha
    Zhou, Haifang
    Lu, Wenyuan
    [J]. COMPUTER ENGINEERING AND TECHNOLOGY, NCCET 2017, 2018, 600 : 22 - 34
  • [3] Design Space Exploration of FPGA-Based Deep Convolutional Neural Networks
    Motamedi, Mohammad
    Gysel, Philipp
    Akella, Venkatesh
    Ghiasi, Soheil
    [J]. 2016 21ST ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2016, : 575 - 580
  • [4] Design Space Exploration for Layer-parallel Execution of Convolutional Neural Networks on CGRAs
    Heidorn, Christian
    Hannig, Frank
    Teich, Jurgen
    [J]. PROCEEDINGS OF THE 23RD INTERNATIONAL WORKSHOP ON SOFTWARE AND COMPILERS FOR EMBEDDED SYSTEMS (SCOPES 2020), 2020, : 26 - 31
  • [5] An Integrated Analysis Framework of Convolutional Neural Network for Embedded Edge Devices
    Lim, Seung-Ho
    Kang, Shin-Hyeok
    Ko, Byeong-Hyun
    Roh, Jaewon
    Lim, Chaemin
    Cho, Sang-Young
    [J]. ELECTRONICS, 2022, 11 (07)
  • [6] Towards Design Space Exploration and Optimization of Fast Algorithms for Convolutional Neural Networks (CNNs) on FPGAs
    Ahmad, Afzal
    Pasha, Muhammad Adeel
    [J]. 2019 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2019, : 1106 - 1111
  • [7] A Design Space Exploration Framework for Deployment of Resource-Constrained Deep Neural Networks
    Zhang, Yan
    Pan, Lei
    Berkowitz, Phillip
    Lee, Mun Wai
    Riggan, Benjamin
    Bhattacharyya, Shuvra S.
    [J]. REAL-TIME IMAGE PROCESSING AND DEEP LEARNING 2024, 2024, 13034
  • [8] Lightweight Convolutional Neural Networks Framework for Really Small TinyML Devices
    Estrebou, Cesar A.
    Fleming, Martin
    Saavedra, Marcos D.
    Adra, Federico
    De Giusti, Armando E.
    [J]. SMART TECHNOLOGIES, SYSTEMS AND APPLICATIONS, SMARTTECH-IC 2021, 2022, 1532 : 3 - 16
  • [9] CNN2Gate: An Implementation of Convolutional Neural Networks Inference on FPGAs with Automated Design Space Exploration
    Ghaffari, Alireza
    Savaria, Yvon
    [J]. ELECTRONICS, 2020, 9 (12) : 1 - 23
  • [10] A Design Space Exploration Methodology for Enabling Tensor Train Decomposition in Edge Devices
    Kokhazadeh, Milad
    Keramidas, Georgios
    Kelefouras, Vasilios
    Stamoulis, Iakovos
    [J]. EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING, AND SIMULATION, SAMOS 2022, 2022, 13511 : 173 - 186