A Sigma-Delta ADC design automation tool with embedded performance estimator

被引：3
|
作者：
Talay, Selcuk [1 ]
Deniz, Engin [1 ,2 ]
Dundar, Gunhan [1 ]
机构：
[1] Bogazici Univ, Dept Elect & Elect Engn, TR-80815 Bebek, Turkey
[2] Dogus Univ, Dept Elect & Commun Engn, Istanbul, Turkey
来源：
INTEGRATION-THE VLSI JOURNAL | 2009年 / 42卷 / 02期
关键词：
Analog-to-digital converter; Sigma-Delta; Design automation; Performance estimator; SWITCHED-CAPACITOR; MODULATORS; SIMULATION; ANALOG;
D O I：
10.1016/j.vlsi.2008.06.002
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A system-level design automation tool for designing discrete time, switched-capacitor, Sigma Delta analog-to-digital converters is presented. The presented work utilizes a performance estimator based on EKV models. The design automation tool takes advantage of high level analytical single-bit and multibit models of the building blocks. With the contribution of the performance estimator module, the tool provides an extensive design environment for designing Sigma-Delta analog-to-digital converters. Developed models and their effects are presented with examples. Design examples for 0.5 and 0.35 mu m technologies are provided for proving the flexibility of the design automation tool. (c) 2008 Elsevier B.V. All rights reserved.
引用
收藏
页码：181 / 192
页数：12
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