A Study on the Fine Pitch Chip Interconnection Using Cu/SnAg Bumps and B-stage Non-conductive Films (NCFs) for 3D-TSV Vertical Interconnection

The increasing demand for high performance integrated circuit devices has been leading the development of 3-D stacking technologies. One of the state-of-art 3-D stacking methods is the through silicon via (TSV) interconnection which may facilitate very high density memories or ASIC modules. Industrial mass production and academic research to use the through silicon via(TSV) in the 3D interconnection has brought the matured technology for forming the TSV in the chip. However, former method using flux and underfill for interconnection between chips have several drawbacks such as flux residues or voids trap along the bonding interface causing reliability issues. As one of the solutions, chip interconnection using Cu/SnAg bump and non-conductive film has been gaining a lot of interest as the one of the promising ways for 3D TSV interconnection. In this paper, a study is made for the relationship between the viscosity of pre applied non-conductive film and loading force to predict the gap change. The existing theories are adapted to predict the gap change of a real chip and a substrate during bonding with using simplified model. A gap changes from real bonding of dies were matched to check the validity of prediction. As a summary, 3D-TSV vertical interconnection using Cu/SnAg bump and wafer-level NCFs was theoretically and experimentally investigated. Through the theoretical investigation, bondings were explained using the rheological properties of NCFs, chip size, and bonding parameters. And the real chip bonding was matched to the prediction from the theory. Therefore, chip bonding using Cu/SnAg bump and NCFs could be the promising solution for the fine pitch TSV interconnection.