Secure Design Flow of FPGA Based RISC-V Implementation

In the process of globalization, heterogeneous SoCs play an important role in an embedded application, security aspects of such a system are crucial. The system is susceptible to many attacks out of which we focus on two main attacks, namely, boot time attacks, where malware are injected to leak information and modify the functionality and rim-time software attacks causing memory corruption. In this paper, we propose a hardware/software-based solution to secure the system integrity by providing secure boot which prevents malicious and unauthorized software dining startup and Information Flow Tracking (IFT) technique to track the spurious data during run-time and preventing buffer overflow attacks. This proposed solution is implemented on the RISC-V and provides a self-authentication mechanism for FPGAs using TPM.