Design, Materials, Process, Fabrication, and Reliability of Fan-Out Wafer-Level Packaging

被引：50

作者：

Lau, John H. ^{[1
]}

Li, Ming ^{[1
]}

Li, Qingqian Margie ^{[1
]}

Xu, Iris ^{[2
]}

Chen, Tony ^{[2
]}

Li, Zhang ^{[2
]}

Tan, Kim Hwee ^{[2
]}

Yong, Qing Xiang ^{[6
]}

Cheng, Zhong ^{[6
]}

Wee, Koh Sau ^{[6
]}

Beica, Rozalia ^{[3
]}

Ko, C. T. ^{[4
]}

Lim, Sze Pei ^{[5
]}

Fan, Nelson ^{[1
]}

Kuah, Eric ^{[1
]}

Kai, Wu ^{[1
]}

Cheung, Yiu-Ming ^{[1
]}

Ng, Eric ^{[1
]}

Xi, Cao ^{[6
]}

Ran, Jiang ^{[6
]}

Yang, Henry ^{[4
]}

Chen, Y. H. ^{[4
]}

Lee, N. C. ^{[5
]}

Tao, Mian ^{[7
]}

Lo, Jeffery ^{[7
]}

Lee, Ricky ^{[7
]}

机构：

[1] ASM Pacific Technol Ltd, Hong Kong, Peoples R China

[2] Jiangyin Changdian Adv Packaging Co Ltd, Jiangyin 214431, Peoples R China

[3] Dow Chem Co USA, Boston, MA 01026 USA

[4] Unimicron Technol Corp, Taipei 304, Taiwan

[5] Indium Corp, Utica, NY 12304 USA

[6] Huawei Technol Co Ltd, Shenzhen 51800, Peoples R China

[7] Hong Kong Univ Sci & Technol, Dept Mech Engn, Hong Kong, Peoples R China

来源：

IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY | 2018年 / 8卷 / 06期

关键词：

Epoxy molding compound; fan-out wafer-level packaging; redistribution layer; reliability;

D O I：

10.1109/TCPMT.2018.2814595

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

The design, materials, process, fabrication, and reliability of fan-out wafer-level packaging (FOWLP) with chip-first and die face-up method are investigated in this paper. Emphasis is placed on the issues and their solutions (such as reconstituted carrier, die-attach film placement, pitch compensation, die shift, epoxy molding compound dispensing, compression molding, warpage, and Cu revealing) during the fabrication of a very large test chip (10 mm x 10 mm x 150 mu m) and test package (13.47 mm x 13.47 mm), and three redistribution layers with the smallest linewidth/spacing = 5 mu m/5 mu m. The FOWLP test package on a six-layer printed circuit board is subjected to 1000 drops of the shock test with a magnitude = 1500 G/ms. Recommendations of process integration and guidelines on FOWLP with chip-first and die face-up are provided.

引用

页码：991 / 1002

页数：12

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