Panel: Physical design and synthesis: Merge or die!

As IC fabrication capabilities extend down to sub-half-micron, the significance of interconnect delay and power dissipation can no longer be ignored. Existing enhancements to synthesis and physical design tools (such as non-linear delay modeling, custom wire load models, back annotation of calculated delays, early floorplanning, post-layout re-mapping and resizing) have not been able to solve the problem. It thus remains that tradeoffs in logical and physical domains must be addressed in an integrated fashion. Huge business opportunities will be lost unless more revolutionary changes to design flow are made. This panel of experts will address the current split between logic synthesis and physical design and its effect on the design flow. It will then discuss possibilities for merging the two, or at least bringing them closer together. In particular, issues such as consistent wire load and timing models and algorithms which must be employed across the design flow, EDA standards and common databases to support the integration of layout and synthesis tools, evolving structured design styles that offer lower wiring overhead, interconnect-driven logic synthesis, and timing driven physical design will, be discussed. Finally, the panel will seek to highlight challenges and potential pitfalls that lie ahead.