Multithreading and Interprocessor Communication in a Dual-Issue Pipelined Processor

This paper describes multithreading and interprocessor communication support in a dual-issue pipelined 32-bit processor for prototyping single-chip multiprocessors in programmable logic. Multithreading support includes multiple register contexts and instructions for thread management. Interprocessor communication support includes a ring network interface embedded in the pipelined datapath with instructions for sending and receiving data through the interface. Synthesis results are presented for a multiprocessor system in an Altera Stratix chip, demonstrating that hardware support for eight threads constitutes 18% of the logic in each processor and the ring interface constitutes less than 3% of the logic.