Evaluation of strained Si/SiGe material for high performance CMOS

The enhanced electrical performance of dual quantum well strained Si/SiGe n-channel MOSFETs has been investigated as a function of SiGe material quality. The higher electron mobility in strained Si compared with bulk Si has been translated into performance gains in terms of device transconductance and on-state drain current exceeding 120% compared with simultaneously fabricated Si controls. Increased performance was demonstrated for a wide range of gate lengths and operating conditions. Trade-offs between optimum device design and SiGe material quality have been investigated. The greatest performance enhancements are achieved through device fabrication on SiGe virtual substrate material grown by low-pressure chemical vapour deposition (LPCVD) at high temperature. Improved surface morphology, defect density and gate oxide quality are found to be the dominating factors in the enhanced performance of the devices compared with strained Si/SiGe MOSFETs fabricated on LPCVD material grown at low temperature. However, even degraded SiGe material arising from low temperature LPCVD growth resulted in strained Si/SiGe n-channel MOSFETs exhibiting significant improvements in device operation compared with conventional Si MOSFETs. The performance advantages offered by strained Si/SiGe devices fabricated on material grown at both low and high temperatures exceed that of a typical Si CMOS technology generation.