Strained SiGe and Si FinFETs for High Performance Logic with SiGe/Si stack on SOI

被引：0

作者：

Ok, I. ^{[1
]}

Akarvardar, K. ^{[2
]}

Lin, S. ^{[3
]}

Baykan, M. ^{[4
]}

Young, C. D. ^{[1
]}

Hung, P. Y. ^{[1
]}

Rodgers, M. P. ^{[5
]}

Bennett, S. ^{[5
]}

Stamper, H. O. ^{[5
]}

Franca, D. L. ^{[5
]}

Yum, J. ^{[6
]}

Nadeau, J. P. ^{[7
]}

Hobbs, C. ^{[1
]}

Kirsch, P. ^{[1
]}

Majhi, P. ^{[1
]}

Jammy, R. ^{[1
]}

机构：

[1] SEMATECH, 257 Fuller Rd, Albany, NY 12203 USA

[2] GlobalFoundries, Milpitas, CA USA

[3] UMC, Crookston, MN 56716 USA

[4] Univ Florida, Gainesville, FL 32611 USA

[5] CNSE, Albany, NY 12203 USA

[6] Univ Texas Austin, Austin, TX 78712 USA

[7] FEI Co, Hillsboro, OR USA

来源：

2010 INTERNATIONAL ELECTRON DEVICES MEETING - TECHNICAL DIGEST | 2010年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this work, we report high performance (I-on similar to 1 mA/mu m at Ioff 100nA/mu m @ 1V Vcc) short channel p-type SiGe/Si FinFETs combining high mobility, low T-inv (scaled High-k w/o Si cap), low R-sd, and process-induced strain. A dual channel scheme for high mobility CMOS FinFETs is demonstrated.

引用

页数：4

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