HASWELL: THE FOURTH-GENERATION INTEL CORE PROCESSOR

被引：181

作者：

Hammarlund, Per ^{[1
]}

Martinez, Alberto J. ^{[1
]}

Bajwa, Atiq A. ^{[1
]}

Hill, David L. ^{[1
]}

Hallnor, Erik ^{[1
]}

Jiang, Hong ^{[2
]}

Dixon, Martin ^{[3
]}

Derr, Michael ^{[1
]}

Hunsaker, Mikal ^{[1
]}

Kumar, Rajesh ^{[1
]}

Osborne, Randy B. ^{[1
]}

Rajwar, Ravi ^{[3
]}

Singhal, Ronak ^{[1
]}

D'Sa, Reynold ^{[4
]}

Chappell, Robert ^{[1
]}

Kaushik, Shiv ^{[5
]}

Chennupaty, Srinivas ^{[1
]}

Jourdan, Stephan ^{[1
]}

Gunther, Steve ^{[1
]}

Piazza, Tom ^{[1
]}

Burton, Ted ^{[4
]}

机构：

[1] Intel, Hillsboro, OR 97124 USA

[2] Intel, Visual & Parallel Comp Grp, Media Architecture Team, Hillsboro, OR 97124 USA

[3] Intel, Product Dev Grp, Hillsboro, OR 97124 USA

[4] Intel, Devices Dev Grp, Hillsboro, OR 97124 USA

[5] Intels Software & Serv Group, Windows OS Div, Santa Clara, CA USA

来源：

IEEE MICRO | 2014年 / 34卷 / 02期

关键词：

Haswell; Instruction set enhancements; Intel core processor; Intel Transactional Synchronization Extensions; Intel TSX; Performance; Power; Power management;

D O I：

10.1109/MM.2014.10

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

HASWELL, THE FOURTH-GENERATION INTEL CORE PROCESSOR ARCHITECTURE, DELIVERS A RANGE OF CLIENT PARTS, A CONVERGED CORE FOR THE CLIENT AND SERVER, AND TECHNOLOGIES USED ACROSS MANY PRODUCTS. IT USES AN OPTIMIZED VERSION OF INTEL 22-NM PROCESS TECHNOLOGY. HASWELL PROVIDES ENHANCEMENTS IN POWER-PERFORMANCE EFFICIENCY, POWER MANAGEMENT, FORM FACTOR AND COST, CORE AND UNCORE MICROARCHITECTURE, AND THE CORE'S INSTRUCTION SET.

引用

页码：6 / 20

页数：15

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