Soft delay error effects in CMOS combinational circuits

Single event upsets (SEUs) are due to high energetic particle strike at sensitive nodes of CMOS combinational circuits. In this paper, we introduce a type of soft errors which manifests as soft delay. The soft delay is temporary delay in CMOS combinational circuits due to high energetic particle strike. We describe soft delay model which enables us to examine delay in CMOS combinational circuits due to particle strike. As technology scales down, the delay due to particle strike increases, and other factors such as V-dd scaling, fanout and transistor strength also contribute to increase the soft delay in CMOS combinational circuits.