Efficient wavelet Architectures using field-programmable logic and residue number system arithmetic

Wavelet transforms are becoming increasingly important as an image processing technology. Their efficient implementation using commercially available VLSI technology is a subject of continuous study and development. This paper presents the implementation using modern Altera APEX20K field-programmable logic (FPL) devices of reduced complexity and high performance wavelet architectures by means of the residue number system (RNS). The improvement is achieved by reducing arithmetic operations to modulo operations executed in parallel over small wordy length channels. The systems are based on index arithmetic over Galois fields and the key for attaining low-complexity and high-throughput is an adequate selection of a small word-width modulus set. These systems are programmable in the sense that their coefficients can be reprogrammed in order to make them more suitable for most of the applications. FPL-efficient converters are also developed and the overhead of the input and output conversion is assessed. The design of a reduced complexity epsilon-CRT converter makes the conversion overhead of this kind of systems be not important for their practical implementation. The proposed structures are compared to traditional systems using 2's complement arithmetic. With this and other innovations, the proposed architectures are about 65% faster than the 2's complement designs and require fewer logic elements in most cases.