Design of Eight Parallel 512-Point MDF FFT/IFFT Processor for WPAN Applications

This paper presents a high-speed FFT algorithm for high data rate wireless personal area network applications. In a wireless personal area network, the FFT/IFFT block leads the major role. Computational requirements of FFT processors are a heavy burden in most real-time applications. From the previous work, it can be recognized that most of the FFT structures follow the divide and conquer algorithms, which improve the computational efficiency. In the proposed model, a new design of 512-point FFT/IFFT processor is derived by mixed approach for a Radix-2(6) algorithm, which has been presented and implemented using the Eight Parallel Multipath Delay Feedback (MDF) architecture. In this work, three distinct complex multiplication approaches are derived; from the analysis, a mixed approach has been proposed to reduce the multiplier complexity and also the equivalent normalized area. The proposed design is compiled and simulated with 90 nm CMOS technology optimized for a 1.2 V supply voltage. The proposed Mixed Radix-2(6) algorithm has been verified and validated using existing architectures. It has been found that the proposed mixed approach for Radix-2(6 )algorithm reduces the normalized area by 8.603% compared with verified architectures. Also, the multiplier complexity is reduced by more than 33% using Canonical Signed Digit constant multiplier. The proposed architecture is suitable for applications like OFDM based WPAN applications at high data processing rates.