A Delay Estimation Method Using Reduced Model of RLC Interconnects

被引：0

作者：

Park, Chang-Woo ^{[1
]}

Jeong, Moon-Sung ^{[1
]}

Kim, Ki-Young ^{[1
]}

Kim, Seok-Yoon ^{[1
]}

机构：

[1] Soongsil Univ, Grad Sch, Dept Comp Sci, Seoul 156743, South Korea

来源：

IEEE EDAPS: 2008 ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM | 2008年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper proposes a new method for delay time calculation in RLC interconnects. This method is simple, yet precise. The proposed method can calculate the delay time of RLC interconnects by simple numerical formula calculation without complex moment calculation using reduced model RLC interconnects. The results using the proposed method for RLC circuits show that the average relative error is within 10% in comparison with HSPICE simulation results.

引用

页码：222 / 225

页数：4

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