Parallel Timing Synchronization Algorithm and Its Implementation in High Speed Wireless Communication Systems

For the sake of high speed wireless communication, this paper proposes a high speed parallel digital timing synchronization algorithm. The algorithm is a joint scheme composes of index-associated rearrangement based parallel FIFOs and a serial digital timing recovery based dual feedback loop. The proposed parallel FIFOs saves 67% LUTs of traditional method. In the feedback loop, to further reduce the complexity, a direct-calculation parallel NCO structure is proposed; meanwhile, to guarantee the high accuracy, an all effective timing errors contained loop filter is proposed. To validate the algorithm, float and fix point simulations were performed on MATLAB platform. The performance loss introduced are less than 0.5 dB and 1 dB respectively, which confirmed the high efficiency of the algorithm. Furthermore, the algorithm is implemented on a Xilinx XC7VX485T FPGA chip, a 20 giga bit per second (Gbps) online 16QAM timing synchronization is achieved at the running frequency of 159.524MHz with two times oversampling.