Thermal sub-modeling of high density interconnect substrates

High-performance integrated circuits require high-leadcount and low-inductance first-level packaging solutions. Suitable packaging options often involve the use of high-density interconnect (HDI, or "microvia") substrate technology. Typical HDI substrates begin with a polymer-glass fiber core laminate, upon which high-density microvia structures are built. The finished substrate can contain hundreds of plated thru-holes (PTHs), microvias, and a dense network of interconnect traces that span four or more layers. The specific arrangement, connection, and layout of these features will affect the effective thermal conductivity of the substrate. This paper extends a previously developed two-dimensional submodeling approach to three-dimensional via structures to allow simple geometric representation of the substrate while accurately determining the out-of-plane conductivity. The technique is applied to two flip-chip plastic ball grid array (FC-PBGA) packages with HDI substrates. The sub-model and package-level modeling results are validated using experimental measurements of die, substrate, and PWB temperature for both convection and conduction cooling environments. Good agreement between simulation and experiment are obtained.