FPGA implementation of a neural network for character recognition

Neural Networks are usually implemented in software on sequential machines but when implemented in hardware, they are extremely fast due to the massive parallelism inherent in the hardware devices. Implementation of Neural Networks in Programmable Logic Devices such as FPGAs (Field Programmable Gate Arrays) gives us more flexibility since these devices are reconfigurable and their design can be altered whenever needed. The design proposed in this paper shows the implementation of perceptron neural network in FPGAs for the character recognition problem. The characters here are the English language alphabets which are input to the network and after training; they are tested for recognition. Each alphabet is tested for three different fonts. After implementation, the simulations are done and performance issues of the design are analyzed. The post-layout simulation gives excellent results even if some noise is introduced to the input patterns.