High Reliability Packaging Technologies and Process for Ultra Low k Flip Chip Devices

被引:0
|
作者
Park, Joonyoung [1 ]
Kim, YunHee [1 ]
Na, SeokHo [1 ]
Kim, JinYoung [1 ]
Lee, ChoonHeung [1 ]
Nicholls, Lou [2 ]
机构
[1] Amkor Technol Inc, 151 Dongil Ro, Seoul 133706, South Korea
[2] Amkor Technol Inc, Tempe, AZ 85284 USA
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暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Ultra-high density chips are required for higher device performance, lower power consumption and a smaller form factor device. The interconnection between the chip and integrated circuit (IC) reflect these higher densities, smaller feature size can induce electrical interference based on layout and material set. Therefore, when new interlayer dielectric (ILD) materials are introduced into next generation process node, the chip package interaction (CPI) must be fully characterized for process compatibility and reliability. Major foundries have used ultra-low dielectric constant (ULK) materials for higher performance devices. But ULK dielectrics have a brittle mechanical nature and are damaged easily from external mechanical or thermal stress. Moreover, as interconnection materials for flip chip devices have changed from collapsible lead-based and tin-silver (SnAg) bumps to more rigid copper (Cu) pillar bumps, the CPI risk has increased as the Cu pillar bumps induce more stress to the ULK dielectric layer. ULK devices require low-stress interconnection methods. Amkor Technology suggests a thermo-compression (TC) bonding with Non-Conductive paste (TCNCP) assembly process to reduce the stress induced between the ULK silicon stack and the substrate. TCNCP utilizes a TC bonder head and heater block for the chip and substrate that minimizes effective CTE mismatch by controlling the reflow temperature more precisely at the chip interface. Maintaining a high temperature difference between chip and substrate is essential in reducing ULK stress from the coefficient of thermal expansion (CTE) mismatch. An approximate 80% improvement in stress levels as compared to conventional mass reflow processes was demonstrated with finite element analysis (FEA) simulation and verified by reliability performance. Amkor Technology applied the TCNCP process in the assembly of a ULK die within a Flip Chip chip scale package (fcCSP). This paper reviews the TCNCP process flow as designed for the ULK device, discusses the reliability results, and proposes guidelines for successful ULK device packaging as process technology migrates to 16/14-nm or 10-nm device nodes.
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页码:1 / 6
页数:6
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