Design of Multiphase Decimation Filter IP Core in Software Radio Receiver

被引：0
|
作者：
Yu, Donghai [1 ]
Wang, Ningchen [1 ]
Gui, Yijun [1 ]
机构：
[1] Southeast Univ, State Key Lab Millimeter Waves, Nanjing 210096, Peoples R China
来源：
2008 4TH INTERNATIONAL CONFERENCE ON WIRELESS COMMUNICATIONS, NETWORKING AND MOBILE COMPUTING, VOLS 1-31 | 2008年
关键词：
Software Radio; Multiphase Decimation Filter; IP Soft-Core; Dynamic Reconfiguration FPGA;
D O I：
暂无
中图分类号：
TN [电子技术、通信技术];
学科分类号：
0809 ;
摘要：
This thesis introduces the design of multiphase decimation filter IP core in software radio receiver in detail. This soft-core could automatically generate Verilog-HDL code with optimized-structure according to input parameters. The application of this core can decrease the design time and cost, and improve reliability; it can also be combined with the dynamic reconfiguration FPGA technology to realize the aim that real-time changing filter performance in order to satisfy the flexible demand of software radio application system.
引用
收藏
页码：1410 / 1414
页数：5
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