Clock jitter in direct RF and IF sampling wireless receivers

被引：3
|
作者：
Chalvatzis, T. [1 ]
Gagnon, E.
Wight, J. S.
机构：
[1] Univ Toronto, Dept Elect & Comp Engn, Toronto, ON, Canada
[2] Nortel Networks, Ottawa, ON, Canada
[3] Carleton Univ, Dept Elect, Ottawa, ON K1S 5B6, Canada
来源：
IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS | 2006年 / 153卷 / 04期
关键词：
D O I：
10.1049/ip-cds:20050154
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The effect of clock jitter on sampling systems is investigated. Analytical expressions are derived for the signal-to-noise ratio (SNR) of an ideal analogue-to-digital converter (ADC). The SNR expressions are based on the autocorrelation function properties of stationary random signals. The power spectral density (PSD) of the analysed signals is baseband/bandpass rectangular and bandpass raised cosine. System level simulations show that the SNR depends on the signal frequency rather than the bandwidth for direct RF and IF sampling. Special focus is given to direct sampling systems with raised cosine PSD (IS-95) in the presence of a blocking signal.
引用
收藏
页码：346 / 350
页数：5
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