Design and Implementation for High Speed LDPC Decoder with Layered Decoding

被引：12
|
作者：
Ding, Hong [1 ]
Yang, Shuai [1 ]
Luo, Wu [1 ]
Dong, Mingke [1 ]
机构：
[1] Peking Univ, Sch EE & CS, Natl Lab Local Fiber Opt Commun Networks & Adv Op, Satellite & Wireless Commun Lab, Beijing 100871, Peoples R China
来源：
2009 WRI INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND MOBILE COMPUTING: CMC 2009, VOL I | 2009年
关键词：
LDPC; layered decoder; highspeed;
D O I：
10.1109/CMC.2009.284
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a layered decoding algorithm for LDPC code and analyzes the advantages and challenge for high speed implementation. Simulation result indicates that layered decoding algorithm converge two times faster than traditional decoding algorithm. A new code, construction scheme aimed to design high speed LDPC decoder with layered decoding algorithm is put forward. This code construction method helps to increase the parallel degree of decoder by suffering with little performance loss. Using the layered decoding algorithm and code construction scheme, a length 2304, rate 1/2 LDPC decoder which can achieve about 768 Mbps information throughput has been implemented on FPGA platform.
引用
收藏
页码：156 / 160
页数：5
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