Impact of On-Chip Multi-Layered Inductor on Signal and Power Integrity of Underlying Power-Ground Net

被引：0
|
作者：
Tsuchiya, Akira [1 ]
Hiratsuka, Akitaka [2 ]
Inoue, Toshiyuki [1 ]
Kishine, Keiji [1 ]
Onodera, Hidetoshi [2 ]
机构：
[1] Univ Shiga Prefecture, Dept Elect Syst Engn, Hikone, Japan
[2] Kyoto Univ, Dept Commun & Comp Engn, Kyoto, Japan
来源：
2018 IEEE 22ND WORKSHOP ON SIGNAL AND POWER INTEGRITY (SPI) | 2018年
关键词：
power integrity; signal integrity; multi-layered inductor;
D O I：
暂无
中图分类号：
TE [石油、天然气工业]; TK [能源与动力工程];
学科分类号：
0807 ; 0820 ;
摘要：
This paper discusses power/ground noise induced by on-chip multi-layered inductors. Employing multi-layered inductors instead of spiral inductors is an effective choice for area-efficient bandwidth enhancement. However the impact of the coupling between multi-layered inductors and underlying circuit is still not clear. We evaluate inductive/capacitive coupling and the impact on the power and the signal integrity. Electromagnetic simulation and circuit simulation show that dense power/ground structure makes the impact of coupling small. The peak-to-peak noise voltage becomes less than 5 mV against 1 V aggressor swing.
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页数：4
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