Ideal Gummel curves simulation of high current gain vertical NPN BIMOS transistor

Within the framework of the optimization of BICMOS technologies, the ideal NPN vertical BIMOS transistor, which combines a silicon bipolar transistor with a MOSFET, is an attractive solution for high integration and other interesting features. The gate electrode is present on the base region of the above bipolar transistor. The different operation modes and electrical performance are described and qualitatively explained. Since it gives the best results on the current gain beta, the so-called hybrid mode is mainly studied. When an appropriated bias is applied to the BIMOS structure, the simulated current gain reaches values of 10(5). To determine the Gummel plots of I-c, I-b versus V-be, V-ce and V-g and to extract the current gain beta versus I-c for different values of the gate bias V-g, three-dimensional (3D) DAVINCI simulations have been performed.