The ideal NPN vertical BIMOS transistor: Analytical model, simulation and experimental results of the collector current

Combining a NPN silicon bipolar transistor with a MOSFET leads to a high collector current in the hybrid mode. As this transistor has already been qualitatively described and as simulation has previously been presented, this paper emphasizes the theoretical study of the collector current, I-c, when the transistor works in the hybrid mode. A model is proposed to demonstrate the great influence of the gate bias and to confirm the previous simulation results. Experimental results were performed with a surface PNP BIMOS transistor sample: they confirm the analytical expression of the collector current in the hybrid mode.