A fast, ultra-low and frequency-scalable power consumption, 10-bit SAR ADC for particle physics detectors

The design and measurements results of a fast 10-bit SAR ADC with ultra-low and scalable with frequency power consumption, developed for readout systems for detectors at future particle physics colliders (ILC, CLIC, LHC Upgrade), are described. A prototype ASIC was designed and fabricated in 130 nm CMOS technology and a wide spectrum of static (INL less than or similar to 0.5 LSB, DNL less than or similar to 0.5 LSB) and dynamic (SINAD similar to 58 dB, ENOB similar to 9.3) measurements was performed to study and quantify the ADC performance. The ADC works in wide 10 kS/s - 40 MS/s sampling frequency range, covering more than three orders of magnitude. In most of the range the power consumption scales linearly with sampling rate with a factor of about 22 mu W/MS/s. A dynamic and asynchronous internal logic makes the ADC very well suited not only for commonly used synchronous sampling but also for applications with asynchronous sampling and/or the ones requiring power cycling, like the experiments at future linear collider (ILC/CLIC). The ADC layout is drawn with a small pitch of 146 mu m to facilitate multi-channel integration. The obtained figure of Merit is in range 32-37 fJ/conversion for sampling frequencies 10-40 MS/s, placing the ADC among the best State of the Art designs with similar technology and specifications.