A 14-bit 8.9GS/s RF DAC in 40nm CMOS achieving >71dBc LTE ACPR at 2.9GHz

被引：0

作者：

Ravinuthula, Vishnu ^{[1
]}

Bright, William ^{[1
]}

Weaver, Mark ^{[1
]}

Maclean, Ken ^{[1
]}

Kaylor, Scott ^{[1
]}

Balasubramanian, Sidharth ^{[1
]}

Coulon, Jesse ^{[1
]}

Keller, Robert ^{[1
]}

Nguyen, Bao ^{[1
]}

Dwobeng, Ebenezer ^{[1
]}

机构：

[1] Texas Instruments Inc, Dallas, TX 75266 USA

来源：

2016 IEEE SYMPOSIUM ON VLSI CIRCUITS (VLSI-CIRCUITS) | 2016年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We show for the first time an 8.9 GS/s RF current-steering DAC, with an on-chip 1:1 Balun, and an 8-lane 12.5 Gbps JESD204B compliant SerDes, with a measured LTE ACPR > 71 dBc in the adjacent 20 MHz band for a 2.9 GHz channel. The DAC has IM3 < -65 dBc for output frequencies up to Nyquist. This performance is accomplished using a novel DAC switch driver and data/dummy-data scheme to minimize the pattern dependent sourcing/sinking of current on the DAC driver supply and ground. The DAC is fabricated in a 40nm dual-oxide CMOS process and dissipates 1.2W, with the contribution of the synthesized digital block and SerDes excluded.

引用

页数：2

共 9 条

[1] A 14-bit 8.9GS/s RF DAC in 40nm CMOS achieving >71dBc LTE ACPR at 2.9GHz
2016, Institute of Electrical and Electronics Engineers Inc., United States (2016-September):
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[7] A 16-bit 10-GS/s Calibration-Free DAC Achieving <-77dBc IM3 up to 4.95GHz in 28nm CMOS
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A 14-bit 8.9GS/s RF DAC in 40nm CMOS achieving &gt;71dBc LTE ACPR at 2.9GHz

A 14-bit 8.9GS/s RF DAC in 40nm CMOS achieving >71dBc LTE ACPR at 2.9GHz