共 50 条
- [41] Test pattern optimization using proper seed selection in mixed-mode technique DELTA 2006: THIRD IEEE INTERNATIONAL WORKSHOP ON ELECTRONIC DESIGN, TEST AND APPLICATIONS, 2006, : 105 - +
- [43] SoC Memory Test Optimization using NXP MTR Solutions 2019 20TH IEEE LATIN AMERICAN TEST SYMPOSIUM (LATS), 2019,
- [44] Optimization of hierarchical SOC test time based on genetic algorithm 2008 INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY & HIGH DENSITY PACKAGING, VOLS 1 AND 2, 2008, : 424 - +
- [45] Design and Optimization of Transparency-Based TAM for SoC Test IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2010, E93D (06): : 1549 - 1559
- [46] TAM design and optimization for transparency-based SoC test 25TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2007, : 381 - +
- [47] A general regression test selection technique World Academy of Science, Engineering and Technology, 2010, 62 : 893 - 897
- [48] VLSI circuit test vector compression technique 2007 IEEE INSTRUMENTATION & MEASUREMENT TECHNOLOGY CONFERENCE, VOLS 1-5, 2007, : 540 - +
- [49] A Regression Test Selection and Prioritization Technique JOURNAL OF INFORMATION PROCESSING SYSTEMS, 2010, 6 (02): : 235 - 252