Built-in self-testing based on compressed 2-dimensional signature analysis

被引:2
|
作者
Cai, CX [1 ]
Wang, XT [1 ]
Peng, YN [1 ]
机构
[1] Tsinghua Univ, Dept Elect Engn, Beijing 100084, Peoples R China
关键词
built-in self-testing; signature analysis; faulty coverage ratio;
D O I
10.1109/ICR.2001.984853
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The designing process of modem electronic systems demands high system reliability and maintainability. In order to perform fault detection, localization and isolation effectively, it is necessary to design a Built-In Self-Testing (BIST) module specific for the corresponding system. This paper presents a BIST method based on the compressed 2-dimensional signature analysis. The principle of compression and performance of test are discussed in detail. Using the presented method, a high Faulty Coverage Ratio (FCR) can be achieved with a short signature compressed in both time domain and space domain. Theoretical analysis shows that this method is reliable and it can be easily implemented in hardware.
引用
收藏
页码:885 / 888
页数:4
相关论文
共 50 条
  • [1] Thermocouples with Built-In Self-testing
    Su Jun
    Orest Kochan
    Roman Kochan
    International Journal of Thermophysics, 2016, 37
  • [2] Built-in self-testing of micropipelines
    Petlin, OA
    Furber, SB
    THIRD INTERNATIONAL SYMPOSIUM ON ADVANCED RESEARCH IN ASYNCHRONOUS CIRCUITS AND SYSTEMS, PROCEEDINGS, 1997, : 22 - 29
  • [3] Thermocouples with Built-In Self-testing
    Jun, Su
    Kochan, Orest
    Kochan, Roman
    INTERNATIONAL JOURNAL OF THERMOPHYSICS, 2016, 37 (04) : 1 - 9
  • [4] ON USING SIGNATURE REGISTERS AS PSEUDORANDOM PATTERN GENERATORS IN BUILT-IN SELF-TESTING
    KIM, K
    HA, DS
    TRONT, JG
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1988, 7 (08) : 919 - 928
  • [5] A Implementation for Built-in Self-Testing of RapidIO by JTAG
    Hu Chunmei
    Zhang Zhenyang
    Guo Yang
    Xu Jingyanan
    2019 IEEE 13TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2019,
  • [6] BUILT-IN HARDWARE FOR THE SELF-TESTING OF LSI CIRCUITS
    YARMOLIK, VN
    SOVIET MICROELECTRONICS, 1986, 15 (01): : 45 - 50
  • [7] BUILT-IN SELF-TESTING RAM - A PRACTICAL ALTERNATIVE
    SALUJA, KK
    SNG, SH
    KINOSHITA, K
    IEEE DESIGN & TEST OF COMPUTERS, 1987, 4 (01): : 42 - 51
  • [8] A concurrent built-in self-test architecture based on a self-testing RAM
    Voyiatzis, L
    Paschalis, A
    Gizopoulos, D
    Kranitis, N
    Halatsis, C
    IEEE TRANSACTIONS ON RELIABILITY, 2005, 54 (01) : 69 - 78
  • [9] Spectral analysis for statistical response compaction during built-in self-testing
    Khan, O
    Bushnell, ML
    INTERNATIONAL TEST CONFERENCE 2004, PROCEEDINGS, 2004, : 67 - 76
  • [10] Self-testing of cores-based embedded systems with built-in hardware
    Das, SR
    IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 2005, 152 (05): : 539 - 546