Comparator-based binary-search ADC architectures for UWB receivers

Recently, modern wireless communication applications have pushed ADCs power consumption into the range of fJ/conversion step by introducing circuit and architectural level enhancements. In this paper we propose improvements to binary-search topologies and demonstrate them on two ADC designs. The first one, a 4-bit ADC, uses 2 (N) - 1 comparators arranged in N stages, and a set of N time-interleaved track-and-holds is introduced along with a pipelined operation of the comparators, leading to an increase of the ADC throughput rate. The second is a 5-bit ADC in which the number of comparators is reduced to N. The reduction is possible because we employ reconfigurable comparator with multiple thresholds, thus splitting the comparison range. As the implementation of accurate threshold voltages has a critical impact on ADC performance, an effective design methodology based on optimization through genetic algorithms was used for the comparators. Monte Carlo simulations performed on the first ADC show that, sampling at 1.5 GSps, the ADC consumes 4.2 mW, providing 3.67 effective bits, leading to a figure of merit (FOM) of 219 fJ/conversion step. With the reduction in the number of comparators, the second ADC consumes 5 mW providing 4.6 effective bits and a FOM of 138 fJ/conversion step at the same sampling rate.