Expression equivalence checking using interval analysis

被引:6
|
作者
Ghodrat, Mohammad Ali [1 ]
Givargis, Tony
Nicolau, Alex
机构
[1] Univ Calif Irvine, Dept Comp Sci, Irvine, CA 92697 USA
[2] Univ Calif Irvine, Ctr Embedded Comp Syst, Irvine, CA 92697 USA
基金
美国国家科学基金会;
关键词
expression equivalence; interval analysis; mutual exclusion;
D O I
10.1109/TVLSI.2006.878471
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Arithmetic expressions are the fundamental building blocks of hardware and software systems. An important problem in computational theory is to decide if two arithmetic expressions are equivalent. However, the general problem of equivalence checking, in digital computers, belongs to the NP Hard class of problems. Moreover, existing general techniques for solving this decision problem are applicable to very simple expressions and impractical when applied to more complex expressions found in programs written in high-level languages. In this paper, we propose a method for solving the arithmetic expression equivalence problem using partial evaluation. In particular, our technique is specifically designed to solve the problem of equivalence checking of arithmetic expressions obtained from high-level language descriptions of hardware/software systems. In our method, we use interval analysis to substantially prune the domain space of arithmetic expressions and limit the evaluation effort to a sufficiently limited set of subspaces. Our results show that the proposed method is fast enough to be of use in practice.
引用
收藏
页码:830 / 842
页数:13
相关论文
共 50 条
  • [21] Application Specified Soft Error Failure Rate Analysis using Sequential Equivalence Checking Techniques
    Li, Tun
    Zhu, Dan
    Li, Sikun
    Guo, Yang
    2013 18TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2013, : 608 - 613
  • [22] Verifying Parallel Code After Refactoring Using Equivalence Checking
    Abadi, Moria
    Keidar-Barner, Sharon
    Pidan, Dmitry
    Veksler, Tatyana
    INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING, 2019, 47 (01) : 59 - 73
  • [23] Using equivalence-checking to verify robustness to denial of service
    Lafrance, Stephane
    COMPUTER NETWORKS, 2006, 50 (09) : 1327 - 1348
  • [24] Using complete-1-distinguishability for FSM equivalence checking
    Ashar, P
    Gupta, A
    Malik, S
    ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2001, 6 (04) : 569 - 590
  • [25] An efficient sequential equivalence checking framework using Boolean Satisfiability
    Zheng, Feijun
    Weng, Yanling
    Yan, Xiaolang
    ASICON 2007: 2007 7TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2007, : 1174 - 1177
  • [26] Logical Equivalence Checking of Asynchronous Circuits Using Commercial Tools
    Saifhashemi, Arash
    Huang, Hsin-Ho
    Bhalerao, Priyanka
    Beerel, Peter A.
    2015 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2015, : 1563 - 1566
  • [27] Verifying Parallel Code After Refactoring Using Equivalence Checking
    Moria Abadi
    Sharon Keidar-Barner
    Dmitry Pidan
    Tatyana Veksler
    International Journal of Parallel Programming, 2019, 47 : 59 - 73
  • [28] Using complete-1-distinguishability for FSM equivalence checking
    Ashar, P
    Gupta, A
    Malik, S
    1996 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN - DIGEST OF TECHNICAL PAPERS, 1996, : 346 - 353
  • [29] Equivalence Checking of Reversible Circuits
    Wille, Robert
    Grosse, Daniel
    Miller, D. Michael
    Drechsler, Rolf
    ISMVL: 2009 39TH IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, 2009, : 324 - +
  • [30] Equivalence Checking for Intelligent Circuits
    Fan, De-Hui
    Ma, Guang-Sheng
    2008 INTERNATIONAL SYMPOSIUM ON INTELLIGENT INFORMATION TECHNOLOGY APPLICATION WORKSHOP: IITA 2008 WORKSHOPS, PROCEEDINGS, 2008, : 785 - 787