Power and Area Optimization for Run-Time Reconfiguration System On Programmable Chip Based on Magnetic Random Access Memory

被引：28

作者：

Zhao, Weisheng ^{[1
,2
]}

Belhaire, Eric ^{[1
,2
]}

Chappert, Claude ^{[1
,2
]}

Mazoyer, Pascale ^{[3
]}

机构：

[1] Univ Paris 11, CNRS, F-91405 Orsay, France

[2] Univ Paris 11, IEF, F-91405 Orsay, France

[3] STMicroelectronics, F-38026 St Martin Dheres, France

来源：

IEEE TRANSACTIONS ON MAGNETICS | 2009年 / 45卷 / 02期

关键词：

Flip-flop; FPGA; low power and low die area; LUT; MRAM; nonvolatile; run-time reconfiguration; SOPC; PERPENDICULAR MRAM; FLIP-FLOPS;

D O I：

10.1109/TMAG.2008.2006872

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In recent years, magnetic random access memory (MRAM) based run-time system on programmable chip (SOPC) has been proposed as a solution to the critical drawbacks of current field programmable gate arrays (FPGAs), such as long (re)boot latency, high standby power, and limits for run time reconfiguration. However, the integration of MRAM in FPGA circuits brings its own problems, including large die area and high dynamic power for the switching circuit. In this paper, we present some solutions to overcome the power and area constraints and thereby improve the performance of MRAM based SOPC. We have done simulations and calculations based on the STMicroelectronics 90 nm design kit and a complete magnetic tunnel junction model.

引用

页码：776 / 780

页数：5

共 35 条

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