Improved PBTI Reliability in Junction-Less FET Fabricated at Low Thermal Budget for 3-D Sequential Integration

被引:3
|
作者
Wu, Zhicheng [1 ,2 ]
Franco, Jacopo [1 ]
Vandooren, Anne [1 ]
Kaczer, Ben [1 ]
Roussel, Philippe [1 ]
Rzepa, Gerhard [3 ]
Grasser, Tibor [3 ]
Linten, Dimitri [1 ]
Groeseneken, Guido [1 ,2 ]
机构
[1] IMEC, Device Reliabil & Elect Characterizat Grp, B-3001 Leuven, Belgium
[2] Katholieke Univ Leuven, ESAT MICAS, B-3001 Leuven, Belgium
[3] Tech Univ Wien, Inst Microelect, A-1040 Vienna, Austria
关键词
3D sequential integration; bias temperature instability; junction-less FET; semiconductor device reliability; variability; mobility; lifetime projection;
D O I
10.1109/TDMR.2019.2906843
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Junction-less FETs are used as top-tier devices in a 3-D sequential integration. Due to the low thermal budget allowed in the 3-D integration, conventional inversion mode FETs show extremely poor BTI reliability. In contrast, a junctionless FET shows improved BTI reliability, which is attributed to the reduced oxide electric field of operation. We observe that the reliability of junction-less FETs can be further improved by increasing the channel doping and/or the channel thickness. Correspondingly, a tradeoff exists between performance (subthreshold slope, carrier mobility), reliability, and variability. This tradeoff is verified in both planar/FinFET structures and can serve as a device optimization matrix. Furthermore, we use the non-radiative multi-phonon (NMP) theory, as implemented in the imec/T.U. Vienna BTI simulation framework "Comphy," to investigate the degradation kinetics and show that the stress/recovery traces measured in inversion mode and junction-less nFETs can be reproduced with the same set of oxide defect parameters. This observation confirms that the reliability improvement in junction-less devices is inherent to their specific operation mode and not related to the different fabrication flows compared to standard inversion mode devices. Based on the calibrated Comphy model, we perform BTI lifetime projections, exposing for junction-less devices a substantial deviation from the commonly used power-law voltage acceleration.
引用
收藏
页码:262 / 267
页数:6
相关论文
共 26 条
  • [21] An edge-defined nano-lithography technique suitable for low thermal budget process and 3-D stackable devices
    Nasrullah, J
    Burr, JB
    Tyler, GL
    2003 THIRD IEEE CONFERENCE ON NANOTECHNOLOGY, VOLS ONE AND TWO, PROCEEDINGS, 2003, : 502 - 505
  • [22] 28nm FDSOI CMOS technology (FEOL and BEOL) thermal stability for 3D Sequential Integration: yield and reliability analysis
    Cavalcante, C.
    Fenouillet-Beranger, C.
    Batude, P.
    Garros, X.
    Federspiel, X.
    Lacord, J.
    Kerdiles, S.
    Royet, A. S.
    Acosta-Alba, P.
    Rozeau, O.
    Barral, V
    Arnaud, F.
    Planes, N.
    Sassoulas, P. O.
    Ghegin, E.
    Beneyton, R.
    Gregoire, M.
    Weber, O.
    Guerin, C.
    Arnaud, L.
    Moreau, S.
    Kies, R.
    Romano, G.
    Rambal, N.
    Magalhaes, A.
    Ghibaudo, G.
    Colinge, J. P.
    Vinet, M.
    Andrieu, F.
    2020 IEEE SYMPOSIUM ON VLSI TECHNOLOGY, 2020,
  • [23] Low Temperature Bump-less Cu-Cu Bonding Enhancement with Self Assembled Monolayer (SAM) Passivation for 3-D Integration
    Lim, Dau Fatt
    Wei, Jun
    Chee Mang Ng
    Tan, Chuan Seng
    2010 PROCEEDINGS 60TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2010, : 1364 - 1369
  • [24] A Review of Low Temperature Process Modules Leading Up to the First (≤500 °C) Planar FDSOI CMOS Devices for 3-D Sequential Integration
    Fenouillet-Beranger, C.
    Brunet, L.
    Batude, P.
    Brevard, L.
    Garros, X.
    Casse, M.
    Lacord, J.
    Sklenard, B.
    Acosta-Alba, P.
    Kerdiles, S.
    Tavernier, A.
    Vizioz, C.
    Besson, P.
    Gassilloud, R.
    Pedini, J. -M.
    Kanyandekwe, J.
    Mazen, F.
    Magalhaes-Lucas, A.
    Cavalcante, C.
    Bosch, D.
    Ribotta, M.
    Lapras, V.
    Vinet, M.
    Andrieu, F.
    Arcamone, J.
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2021, 68 (07) : 3142 - 3148
  • [25] Analysis of TDDB lifetime projection in low thermal budget HfO2/SiO2 stacks for sequential 3D integrations
    Vici, A.
    Degraeve, R.
    Roussel, P. J.
    Franco, J.
    Kaczer, B.
    De Wolf, I.
    2023 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, IRPS, 2023,
  • [26] Comparison of Mechanical Stresses of Cu Through-Silicon Via (TSV) Samples Fabricated by Hynix vs. SEMATECH using Synchrotron X-ray Microdiffraction for 3-D Integration and Reliability
    Budiman, A. S.
    Shin, H.
    Kim, B. -J.
    Hwang, S. -H.
    Son, H. -Y.
    Suh, M. -S.
    Chung, Q. -H.
    Byun, K. -Y.
    Joo, Y. -C.
    Caramto, R.
    Smith, L.
    Kunz, M.
    Tamura, N.
    2012 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE (IITC), 2012,